When designing increasingly complex processors or IC chips such as Application-Specific ICs (ASICs) and system-on-chips (SoC's), functional verification has proven to be a major bottleneck in achieving time-to-market goals. Many companies now realize that functional verification of complex chips has become an inefficient, unwieldy, and incomplete process. Design teams report that functional verification of medium- to large-complexity processors, ASICs or SOC's may consume over 70% of the project's manpower, schedule and budget. In spite of the time and resources consumed by functional verification, it is still often incomplete, allowing design bugs to go undetected. Improved functional verification can cut costs, improve design quality and accelerate time-to-market, as well as allowing companies to sharply increase the productivity of precious verification personnel.
The design process for a chip starts with the creation of a functional specification for the design. Once the functional specification has been completed, the verification team typically creates a test plan that specifies the design features and functions to be tested at both the block and system levels. The verification team then creates tests such as deterministic tests and weighted-random tests to verify design functionality until all test plan requirements have been met. The verification process involves developing and simulating tests that are used to determine whether design components (e.g., processor units, I/O busses, resources, functions, etc.) behave according to their functional specification in a process known as functional simulation. Functional verification is often an iterative process where the entire system (or at least all its major features) is tested on a continuous basis for the duration of the design process. Functional verification is typically completed before fabrication, as finding and fixing errors, or bugs, after fabrication proves to be time-consuming and expensive. Functional coverage is the study and analysis of the quality and completeness of functional verification. It includes statistical, stochastic and heuristic analysis of functional verification progress and completeness.
Formal methods can be applied to the design for verification of design features, as well as identifying design connectivity and signal propagation characteristics. In most such cases, a set of formal rules or design behavior specifications are defined and applied against a compiled model of the design to identify any deviation from the formal specification (rules). Some tools can generate a set of checkers and monitors from the formal rules which can then be used along with the simulation-based verification.
Software tools have been developed to help designers and testers with the functional verification process. A design under test (DUT) may be described using a hardware description language (HDL) such as VHSIC (Very High Speed Integrated Circuits) HDL (VHDL) or Verilog. Automation tools such as Verisity Design, Inc.'s (Verisity) Specman testbench automation software provide an environment for generation of functional tests, data and temporal checking, functional coverage analysis, and HDL simulation control.
Some design components require sophisticated modeling in order to properly simulate their performance (and thus to complete functional verification). Functional verification of a high-speed, self-aligning, elastic I/O design, for example, poses problems with existing verification environments. An elastic interface design, in one example, allows an external receiver communicating with a similar elastic interface transmitter to deskew (line up) the data bits within each clock-data group to account for path variance across the bus, to align separate clock-data groups after they have been deskewed to compensate for noise, to adjust for non-ideal duty cycles and voltage reference (VRef) distortion, and to make dynamic recalibrations to keep the bus aligned and sampling correctly during variations of voltage and temperature. Current environments are unable to satisfactorily model many aspects of elastic I/O bus designs, such as gradual drift of noise and distortion parameters. There is, therefore, a need for an improved mechanism for functional simulation and verification of components such as high-speed bus designs.